Electronic sensing system for selectively energizing and de-energizing apparatus

ABSTRACT

THE ELECTRONIC SENSING SYSTEM SELECTIVELY ENERGIZES AN ELECTRICAL APPARATUS A PREDETERMINED TIME AFTER THE ELECTRICAL POWER IS APPLIED TO THE SYSTEM AND IN SYNCHRONISM WITH A SIGNAL INDICATING THE APPARATUS IS READY TO BE ENERGIZED. THE ELECTRICAL APPARATUS IS DE-ENERGIZED IN RESPONSE TO BOTH A SUDDEN DECREASE IN AMPLITUDE OF A MONITORED VOLTAGE WHICH ACTIVATES A TRIGGER CIRCUIT, AND IN SYNCHRONISM WITH A SUBSEQUENT SIGNAL INDICATING THE APPARATUS IS READY TO BE DE-ENERGIZED. A SENSING CIRCUIT COMPARES THE VOLTAGE BEING MONITORED WITH A REFERENCE DERIVED FROM THIS VOLTAGE TO ACTIVATE THE TRIGGER CIRCUIT.

W. MILLEKER ET AL Feb. 2, 1971 L 3,560,861

' ELECTRONIC sENsING SYSTEM FOR SELECTIVELY ENERGIZING ANDIDE-ENERGIZING APPARATUS Filed Jan. 16, 1969 A Inventors WILLIAMMILLEKER RONALD J. SEKULA United States Patent Oce ELECTRONIC SENSINGSYSTEM FOR SELEC- TIVELY ENERGIZING AND DE-ENERGIZ- ING APPARATUSWilliam Milleker and Ronald J. Sekula, Chicago, Ill., assignors toMotorola, Inc., Franklin Park, lll., a corporation of Illinois FiledJan. 16, 1969, Ser. No. 791,555 Int. Cl. H03k 17/28 U.S. Cl. 328-74 6Claims ABSTRACT F THE DISCLOSURE BACKGROUND OF THE INVENTION There aremany applications for a system which can be used to enable anddisenableelectrical and mechanical apparatus whose operation is begunand terminated according to happenings which can either directly orindirectly produce electrical signals. For example, an electromechanicalapparatus such as a washing machine that is programmable to go throughvarious modes of operation must be controlled so that some portions ofthe machine are selectively enabled at the beginning of one mode andselectively disenabled at the end of another mode. Alternatively, theapparatus can be electronic in nature such as a magnetic core memoryexercitator which writes data into and reads data out of a core memoryin synchronism with signals provided by the system with which the corememory is used.

It is well-known to use a matrix of magnetic cores as a binary memory inelectrical systems such as calculators, data processors, and displaysystems. This type of core memory can be used to supply binary data to adisplay system which is comprised of a character generator operating incooperation with a television (TV) monitor receiver to displayalphanumeric information. At the beginning of a horizontal scan line ofthe beam in the cathode ray tube (CRT) of the TV receiver, theexercitator reads binary data out of the core memory and places it in adisplay register which includes a temporary memory whose retention ofbinary data is dependent on the continuous application of externalenergy. The binary data is then selectively read out of the displayregister and used to generate an alpha numeric display on the CRT. Thedata is also returned to the core memory with each write operation.

There are problems associated with the de-energization and energizationof this kind of an exercitator. When the primary power is interruptedfor any cause, the DC operating power derived therefrom willsubsequently decay until it is below a critical level at which theoperation of the memory exercitator and display register becomessporatic. Consequently, data stored in the temporary memory of thedisplay register after the time of primary power interruption might bedestroyed or lost unless the exercitator is disenabled at the end of thehorizontal scan line of the CRT when all the data is in the core memory.Also, when the primary power is first applied to the DC 3,560,861Patented Feb. 2, 1971 power supplies, the amplitude of their outputvoltages will be unstable for a short period of time thereby resultingin intermittent operation of the character display system which mightresult in the loss of data if the exercitator is enabled during thisperiod of time.

BRIEF SUMMARY OF THE INVENTION It is an object of the invention toprovide an inexpensive, simple, and reliable sensing system to applyenabling and disenabling signals to electrical apparatus in synchronismwith predetermined happenings in the apparatus.

It is another object of the present invention to apply a disenablingsignal to the electrical apparatus after its primary power isinterrupted, in coincidence with a synchronizing signal, and before theamplitude of a monitored voltage decays to a critical level.

It is a further object of the present invention to apply an enablingsignal to the electrical apparatus a predetermined time after theoperating power is applied thereto and in coincidence with asynchronizing signal so that the power supplies and other circuitry havetime to stabilize.

In order that its advantages might be appreciated, the invention isdescribed in relation to its operation as a power sensing circuit toenable and disenable a core memory exercitator in accordance withsynchronizing (sync) pulses, and in response to changes in the amplitudeof a primary supply voltage providing power to DC supplies, which inturn provide operating power for the exercitator. The sensing operationresulting in the selective disenablement of the exercitator depends inpart on the substantially different rates at which the output voltagesof two DC power supplies decrease after the primary voltage has beendisconnected. The first power supply provides operating and biasvoltages to the exercitator and to the sensing system of the invention.The second power supply provides an output voltage to be monitored toone input of the sensing system and a reference voltage to anotherinput. For use in other applications, the monitored voltage could bederived elsewhere. If the primary power is interrupted for any cause,the amplitude of the monitored voltage of the second power supplydecreases more rapidly than the amplitude of the exercitator operatingvoltage of the first power supply.

In the sensing system, the amplitude of the monitored voltage isconstantly compared to the amplitude of the reference voltage by adifferential amplifier to produce a voltage that is dependent on thedifference therebetween. Whenever the amplitude of this differencevoltage exceeds a predetermined amount, a DC danger voltage is deliveredto one input of a two input gate, and sync signals are applied to theother input. The next sync pulse after the DC danger voltage causes adanger signal to be applied from the output of the gate to set first andsecond bistable multivibrators (bistables). The setting of the firstbistable disenables the memory exercitator at an instant in timecorresponding to the occurrence of the sync signal. At this time all ofthe binary data is permanently stored in the core memory matrix, and theoperating and bias voltages have not decayed below their criticalamplitudes.

-A feature of the invention is the provision wherein the referencevoltage is directly derived from the voltage to be monitored. Themonitored voltage is directly connected to the first of two inputs of acomparator trigger circuit and indirectly connected through a diode tothe second input thereby developing a reference voltage across acapacitor which is connected between the second input and ground. When'the amplitude of the monitored voltage at the first input of thecomparator suddenly decreases, the reference voltage at the second inputcannot correspondingly suddenly decrease because the capacitor cannotrapidly discharge through the reverse biased diode or through the highinput impedance of the comparator trigger circuit. The amplitudedifference between the reference and the monitored voltages is sensed bythe comparator to provide a trigger or danger voltage which is utilizedto disenable the exercitator as described above.

The circuit for energizing the core memory exercitator includes aunijunction 4timer that begins its timing cycle with the initialapplication of bias power for the exercitator. This initial applicationof power sets the two bistables thereby temporarily keeping theexerci-tator from operating. After a predetermined interval of time,during which the amplitude of the DC power supply output voltages andother voltages can stabilize, the timer ends its timing cycle andproduces a delayed output pulse which resets the second bistable toapply a DC ready voltage to one input of a two input gate. Sync signalsare continuously applied to the other input of the gate. Consequently,upon the application of the next sync signal after the DC ready voltage,la ready signal at the output of the gate resets the first bistable andthereby enables the exercitator. Data is thus kept in the core memory apredetermined interval of time after the power supply voltages areapplied to the exercitator and until the occurrence of a sync signalwhich signifies that the character generator is ready to receive datafrom the exercitator.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. l is a block diagram of thesystem of the invention; and

FIG. 2 is a schematic diagram of the system shown by the block diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIGS. 1 and 2, thesensing system of the invention first will be described in relation toits enabling function. Power from primary power Isupply is connectedthrough switch 12 to first DC power supply 14 which has output terminals16, 1:8 and 20, and to second DC power supply 22. Output 1'6 of powersupply 14 is grounded, and output 18 provides operating power of a firstpolarity to bias terminals 24 and 26 of bistables 27 and 28, and toterminal 29 of the comparator trigger circuit 30. To simplify thedrawing the connecting lines from output 18 of power supply 14 are notshown. Output terminal provides operating power of -the second polaritythrough diode 34 and across `capacitor 36 to the logic circuitry of theinvention land to the initial condition determining network comprised ofthe serial connection of resistor 38 and capacitor 40. Since capacitor40 is initially uncharged, a ground potenti-al is initially appliedrespectively through diodes |42 and 44 to set the initial voltage outputlevels at output terminals 46 and 4 8of bistables 27 and 28 to lowlevels. By regenerative action the low level at output terminal 48forces a high level at output terminal y49 of bistable 28 which renderthe memory exercitator 50 connected thereto inoperative so that it doesnot read data from or write data into a core memory. v

Since output terminal 46 of bistable 27 is connected to the input ofinverter 51, the initial low level at output terminal 46 provides a highat output terminal 52 of the inverter which is connected to the input ofunijunction timer 54. The high level at terminal 52 enables timer 54 tobegin its timing cycle during which the output voltages of powersupplies 14 and 22 stabilize and reference voltage capacitor 58, whichis connected through resistor 59 to input 60 0f comparator trigger 30,charges up. After a predetermined interval of time, unijunction timer 54completes its timing cycle and produces a pulse at its output terminal`56 which is applied through its connection to input terminal y61 vthusresetting bistable 27 and thereby resulting in a high level at outputterminal 46 which is connected back through inverter 51 to pro- 4 vide alow level at terminal 52 that deactivates timer S4. Also when the outputterminal 46 is at a high level the level at output terminal 62 is lowand this low level or DC ready voltage is applied to input terminal 64of first NAND gate 66. Sync signals are applied to input `68 of NANDgate 66. Consequently, the next sync signal occurring after the DC readyvoltage produces a ready signal at NAND gate output terminal 70 which isconnected to input 72 of bistable 28 thus resetting this bistable tocause a low level or `an enabling signal at output 49 which rendersexercitator '50 operative; and, as a result it now can read data from orwrite data into a core memory.

Therefore, the exercitator is enabled in synchronism with the yfirstsync signal occurring a predetermined interval of time after theapplication of the power to the invention. This interval of time allowsthe power supplies to stabilize and the reference voltage to bedeveloped across capacitor 5'8.

The invention will now be described in relation to its disenablingfunction. Output 73 of power supply 22 is grounded, and output 74 isconnected to input 76 of the sensing circuit. When the amplitude of thevoltage of primary power supply 10 decays rapidly or switch 12 isopened, the output voltage of power supply 22 decreases more rapidlythan the output voltages of DC power supply 14. The output voltage ofpower supply 22 is constantly monitored by comparing it to a referencevoltage to sense when primary power supply 10 has a reduced voltage Vasdescribed below.

Input terminal 76 is connected to a filter network comprised of inductor82 and capacitor 84 which together form a low pass filter foreliminating any spurious noise signals applied to terminal 76. Themonitored voltage across capacitor y84 is applied through currentlimiting resistor `86 to input 88 of comparator trigger circuit 30.Also, the monitored voltage across capacitor 84 is applied through diodel90# to charge 'capacitor 58 to a reference voltage which is appliedthrough current limiting resistor 59 to input 60 of comparator triggercircuit 30. While the system of the invention is operative resistor 96provides a high resistance current path for diode 90, and after thesystem becomes inoperative resistor 96 provides a high resistancedischarge path for capacitor 58.

When the primary volt-age from primary power supply 410 rapidlydecreases, or when power supply 22 fails, the amplitude of the voltageapplied to comparator trigger input terminal 88 will likewise decrease.The reference voltage at input terminal `60, however, cannot accordinglydecrease because capacitor 58 is unable to rapidly discharge through thehigh resistance of resistor 96 or through the high input impedance ofcomparator trigger 30 or through diode 90 which will be reversed biasedbecause the voltage across capacitor 58 will have a greater amplitudethan the decaying voltage of output 74 of power supply 22.

Included in comparator trigger circuit 30 is a high gain differentialamplifier having essentially a trigger circuit output. The output of thedifferential amplifier is dependent on the difference between theamplitudes of the monitored voltage lat input terminal 88 and thereference voltage at terminal 60. When the amplitude of the voltage(between inputs 60 and 88) exceeds a predetermined limit thedifferential amplifier circuit output will produce a DC danger voltageor low level at output 96 which is connected to one input 98 of twoinput NAND gate .100. Since sync signals are applied continuously to theother input 102 of gate 100, the next sync signal after the DC dangervoltage causes a danger signal at output 104 of NAND gate 100. Thissignal is connected to the second inputs 108 and 110 of bistables 27 and28 to set the same. As a result, a high level at output 49 of bistable28 disenables eXercitator 50.

Thus the exercitator is disenabled after a monitored voltage, which inthis case is the output voltage of power supply 22, has decreased belowa predetermined amplitude but before the output voltages provided by anyof the power supplies decrease to a critical value below which theexercitator is subject to sporatic operation. The exercitator isdisenabled in synchronism with a sync signal applied to input 102 ofgate 100 which occurs at a time when all the data has been returned to acore memory and will be preserved therein.

What has been described, therefore, is a simple sensing system forselectively enabling and disenabling a core memory exercitator. Thereare many other applications where the sensing system can be used toadvantage for providing control of electrical apparatus in response topredetermined happenings which are manifested by electrical signals.Furthermore, the invention is easy to build, reliable, and portions ofits can utilize integrated circuits to reduce costs.

What is claimed is:

1. An electrical system for respectively providing enabling anddisenabling voltages to electrical -apparatus in synchronism withselected first and second signals provided to the electrical system,such electrical system including in combination, electrical power supplymeans providing an operating voltage, timing means for producing a rstoutput pulse an interval of time after the operating voltage from saidelectrical power supply means is applied to the system, switching meansresponsive to said first output pulse and to the first signal occurringafter said first output pulse to provide the enabling voltage, voltagesupply means providing a direct current voltage, means deriving areference voltage from said direct current voltage, comparator triggermeans having first and second inputs, means applying said referencevoltage to said rst input, means applying said direct current voltage tosaid second input, said comparator trigger means being responsive tochange in the amplitude of said direct current voltage to provide asecond output pulse when said amplitude changes a predetermined amountwith respect to said reference volt-age, said switching means beingresponsive to said second output pulse and to the second signal toproduce the disenabling voltage.

2. An electrical system in accordance with claim l1 further including,capacitor means for providing said reference voltage, electron controlmeans connecting the direct current voltage to said capacitor means tocharge the same to provide said reference voltage, said electron controlmeans acting to isolate the amplitude of said reference voltage on saidcapacitor means from the amplitude of the direct current voltage whenthe Iamplitude of the direct current voltage diminishes a predeterminedamount at a given rate.

3. The electrical system of claim 1 wherein said switching meansincludes two bistable multivibrator means, and two gating means whichcooperate with said two bistable multivibrator means to provide saidenabling and dis-enabling voltages at an output of one of said bistablemultivibrator means.

4. The electrical system of claim 3 further including, an electricalnetwork having resistive means and capacitive means connected in series,said electrical network being connected between said electrical powersupply means and ground, both of said bistable multivibrator means beingconnected to the junction of said resistive means and said capacitivemeans, said network determining the initial conditions of the outputvoltage levels of both of said bistable multivibrator means.

5. An electrical system for preserving data stored in a memory byselectively applying enabling yand disenabling signals to the memoryexercitation means at intervals of time after primary supply means forthe memory exercitation means is respectively operative andinoper-ative, and wherein first and second synchronizing signals areprovided to the electrical system, such electrical system including incombination, iirst and second direct current power supply meansobtaining energy from the primary power supply means, said first directcurrent power supply means having an output voltage amplitude thatdecreases at a substantially slower rate than the output voltageamplitude of said second power supply means in response to decrease inthe voltage amplitude of the primary supply means, said first directcurrent power supply means providing operating power for the electricalsystem and the memory exercitation means, said second direct currentpower supply means providing a monitored direct current voltage, sensingcircuit means -responsive to the first synchronizing signal to producean enabling signal to render the memory exercitation means operative,said sensing circuit means being responsive also to a predetermineddecay of the amplitude of said monitored direct current voltage and to asecond synchronizing signal occurring thereafter to produce adisenabling signal to render the memory exercitation means inoperative.

6. An electrical system corresponding to claim 5 wherein said iirst andsecond power supply means provide output voltages having amplitudeswhich stabilize an interval of time after the primary power source isconnected thereto, and wherein said sensing circuit means includestiming means responsive to the application of operating power to thememory exercitation means to thereby provide a delayed output pulse,switching means connected to said timing means and responsive to saiddelayed output pulse to produce a triggering voltage, and gating meansconnected to said switching means and producing said enabling signal inresponse to the application thereto of said triggering voltage and thenext subsequently occurring first synchronizing signal.

References Cited UNITED STATES PATENTS 2,914,704 11/1959 Nesler et alS17-31X 3,320,440 5/1967 Reed 235-153X DONALD D. FORRER, PrimaryExaminer R. C. WOODBRIDGE, Assistant Examiner U.S. Cl. X.R. 23S-153;307-130, 301; 317-22, 31; 328-72

